1. Field of the Invention
The invention relates to design of an integrated circuit (IC), for fabrication in a wafer of semiconductor material. More specifically, the invention relates to a method and an apparatus to reduce pessimism in identification of undesirable electrical interaction (called “capacitive crosstalk”) which may arise between wires and/or devices that are physically placed and/or routed adjacent to one another in an IC design.
2. Related Art
Crosstalk is an undesirable electrical interaction between two or more physically adjacent wires in an integrated circuit (IC) device, due to capacitive cross-coupling 101 (also called “crosstalk”) illustrated in FIG. 1A. As IC fabrication technologies advance toward smaller geometries, wires in the IC device become closer and taller, thus increasing the capacitance due to cross-coupling between nets in the IC device. At the same time, parasitic capacitance 102 (FIG. 1A) to the substrate becomes less, as interconnections become narrower, and cell delays are reduced as transistors become smaller.
Prior art software tools in the field of electronic design automation (EDA) are available to design circuitry (see step 103 in FIG. 1B), to place and route the circuitry for fabrication into a die (see step 104), perform parasitic extraction and static timing analysis (see step 105) and report on delays in signals due to crosstalk (see step 106). Parasitic extraction in step 105 can be either variation aware or corner based. For example, a tool called Star-RCXT VX available from Synopsys, Inc. of Mountain View Calif. can be used to report can be used for variation aware parasitic extraction, and the tool Star-RCXT itself can be used to extract corner specific parasitics. Similarly, static timing analysis in step 105 can be variation aware (e.g. using statistical static timing analysis) or corner specific (e.g. using voltage, temperature or process corners). For example, a tool called “PrimeTime®SI” available from Synopsys, Inc. can be used to report on delay changes and static noise. Another tool called “PrimeTime®VX” available from Synopsys, Inc. can be used for statistical static timing analysis. Note that both “PrimeTime®SI” and “PrimeTime®VX” are enhancements to a static timing analysis tool called PrimeTime® also available from Synopsys, Inc. A timing report which is generated by crosstalk analysis typically identifies violations in setup time, hold time and/or signal arrival used to generate an Engineering Change Order (ECO) as illustrated by step 107 (FIG. 1B). If there are no violations in step 108, the design is signed off, followed by resolution, and tape out, for fabrication of a wafer.
An aggressor net 111 (FIG. 1C) typically injects a crosstalk glitch onto a victim net 112 through one or more coupling capacitors 113. The crosstalk glitch impacts the delay (FIG. 1D) of victim net 112 by increasing or decreasing it. The amount of this increase or decrease is called “crosstalk delay” (FIG. 1D). Such a victim net 112 is typically present in a path (called “critical path”) in the IC device consisting of timing nodes which represent pins on the path. A timing requirement on such a path may be expressed as the latest (or the earliest) time at which a signal can arrive without making the clock cycle longer (or shorter) than desired. Specifically, the arrival time is signal propagation time from a given starting point. Another timing requirement may be expressed in the form of slack which is the difference between the required time and the arrival time. When the slack of a path is negative, the path has a timing violation.
Timing violations are typically identified by performing crosstalk analysis, which checks if there is a timing overlap between changes in signals in adjacent nets. Analyzing whether changes in two signals have timing overlap is memory and processor intensive. Accordingly, for a pre-determined design corner e.g. process, voltage and temperature, certain prior art techniques identify two extremes, e.g. the slowest possible arrival time (i.e. the largest arrival time) and the fastest possible arrival time (i.e. the slowest arrival time), to form a window 115 (FIG. 1E) in which an aggressor's signal is expected to arrive (“aggressor window”) at the aggressor's output. Similarly, another window 114 (FIG. 1E) is formed, in which a victim's signal is expected to arrive (“victim window”) at the victim's output. As shown in FIG. 1E, victim window 114 is defined by the earliest arrival time Tvearly (i.e. the fastest possible arrival time), and the latest arrival time Tvlate (i.e. the slowest possible arrival time) of a signal at the victim's input (or output depending on the embodiment). Similarly, aggressor's window 115 is defined by the earliest arrival time Taearly and the latest arrival time Talate. For further information on such methods, see, for example, an article entitled “Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis” by Tong Xiao and Malgorzata Marek-Sadowska, VLSI Design, 2002 Vol. 15 (3), pp. 647-666, which is incorporated by reference herein in its entirety as background. See also US Patent Application Publication 2002/0104064 filed on Aug. 7, 2001, entitled “Electronic Circuit Device and Its Design Method” published on Aug. 1, 2002 by Yasuhiko Sasaki and Naoki Kato, which is also incorporated by reference herein in its entirety as background.
Note that the graph shown in FIG. 1E is not specific to any corner or variation (e.g. in voltage, temperature or process parameter). Instead, windows 114 and 115 in FIG. 1E arise due to inherent characteristics (such as asymmetry) of devices in the circuitry upstream from the victim and the aggressor (i.e. upstream from the coupled stage). In contrast, FIG. 1F illustrates a graph 141 at a fast corner (e.g. minimum delays throughout), and another graph 142 at a slow corner (e.g. maximum delays throughout). Note that a victim net's late edge Tvlate in the fast corner may occur (e.g. at time T3 in FIG. 1F) well in advance of that same victim's early edge Tvearly in the slow corner (e.g. at time T6 in FIG. 1F). Hence, if two victim windows 116 and 118 are combined, a combined victim window may extend from the earliest edge at time T1 (in the fast corner) to the latest edge at time T9 (in the slow corner). However, a combined victim window 144 may also be formed based on user-specified limits, such as 3σ, on probability density functions 145 and 146 of the victim signal's fastest and slowest arrival times, as discussed below, Similarly, aggressor windows 117 and 119 may be combined to form combined window 147.
Accordingly, to reduce pessimism inherent in checking if there is overlap between an aggressor window 115 and a victim window 114, it is now necessary to take into account changes in one or more physical characteristics that may vary depending on a number of factors, such as global and local variation in the process of fabricating the IC device, as a die in a wafer. Specifically, wafer fabrication process variations may be modeled by distributions of probability that in turn result in probability density (across all dies in the wafer) in the time required by a signal to reach a specific output of a circuit in each die, such as distribution 121 (FIG. 1G) of min arrival time at an output (of victim net 112). Similarly, another probability density (also across all dies in the wafer) 122 is available for the max arrival time at the same output (of victim net 112). Hence, certain prior art techniques use the two probability density functions 121 and 122 of arrival times (FIG. 1G), to construct a window 123 (FIG. 1G) having an early side at −3σ from the mid-point (i.e. mean 121C) of the min probability density 121 and a late side at +3σ from the midpoint (i.e. mean 122C) of the max probability density 122. The window 123 is also called a 3σ window, and this window is for the victim, i.e. a victim timing window. A similar 3σ window 125 is constructed and used for the aggressor, i.e. an aggressor timing window. 3σ is an arbitrary value that a user may specify to a tool that performs variation aware timing analysis. Any percentile value on the probability density function maybe used to represent the arrival window.
Due to the fact that variation aware windows (3σ windows) 123 and 125 (FIG. 1G) include the effects of process variations, they tend to be larger than corresponding individual windows 114 and 115 (FIG. 1E) of an individual die. The inventors of the current patent application have found that prior art windows (such as 3σ windows), which are used by some prior art tools, still make these tools pessimistic in identifying aggressors during crosstalk analysis. Specifically, the current inventors find that use of prior art windows can result in identification of false aggressors. For example, the current inventors note that aggressors may be identified as being present in a victim and aggressors combination even if they do not really exist, due to the manner in which 3σ windows 123 and 125 overlap. The overlap is illustrated in FIG. 1H, which shows the probability density functions for the combination where individual timing windows of a victim and its aggressor in each individual die do not in fact overlap one another. The just-described situation is illustrated in FIG. 1I, wherein timing windows 123A and 123B representing the victim net timing windows for two die samples do not overlap the corresponding timing windows 124A and 124B representing the aggressor net timing windows for the same two die samples. Nonetheless, when two or more victim windows 123A and 123B are combined to form a single window 123C, then the combined window 123C extends up to time T7 and overlaps with another combined window 125C that starts at time T6 formed by combining aggressor windows 125A and 125B. The current inventors note that use of combined windows 123C and 125C in crosstalk overlap analysis identifies an overlap in period T7-T6, although there is in fact no overlap between the individual windows 123A, 125A respectively of victim and aggressor pair in one die and similarly no overlap in the individual windows 123B, 125B respectively of victim and aggressor pair in another die.
US Patent Application Publication 2006/0112359 filed on Nov. 22, 2004 by Becer et al, entitled “Pessimism Reduction in Crosstalk Noise Aware Static Timing Analysis”, and published on May 25, 2006 is incorporated by reference herein in its entirety as background. As per this patent publication, processes and systems for reducing pessimism in cross talk noise aware static timing analysis (and thus resulting false path failures) use either or both of effective delta delay noise and path based delay noise analysis. Effective delta delay determines an impact on victim timing of an action by aggressors that occur during a region where victim and aggressor timing windows overlap and determines an effective delta delay corresponding to any portion of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time, i.e. during a switching time window when uncertainty is included.
The current inventors believe that US 2006/0112359 does not disclose reducing pessimism in variation aware crosstalk analysis, as described below.